The Advantages of Actively Loaded MOSFET

images-7The previous article presented the “drain-resistor problem”: We need a larger drain resistor to achieve higher gain, but more drain resistance means a lower DC bias voltage at the output node.

This is a problem because the output voltage is also the MOSFET’s drain voltage, and a lower drain voltage corresponds to a higher risk of pushing the FET out of saturation and into the triode region. We suggested that a current source might resolve this problem by providing high gain without negatively affecting the bias conditions.

The following diagram gives you an idea of the improved biasing situation associated with the use of a current mirror instead of drain resistors.

We have not yet discussed the small-signal resistance of the active-load current mirror, so for now you’ll just have to believe me when I tell you that it is quite high. But as you can see in the circuit diagram, this large small-signal resistance does not apply to the biasing conditions: The bias voltage at the output node is determined by whatever gate-to-source voltage corresponds to Q3’s drain current.

If we consider that this drain current is not particularly large and that Q3’s threshold voltage is maybe 0.7 V, we can guess that the magnitude of VGS will be quite small relative to the high gain resulting from the current mirror’s large small-signal resistance.

Let’s confirm this guess via simulation. Here is the LTspice circuit, with the bias voltage labeled:

(The SPICE models for the FETs can be downloaded here.) This simulation demonstrates that the current mirror’s large small-signal resistance (and thus high gain) does not require a large DC voltage drop. With this particular circuit, Q3 can generate current equal to IBIAS/2 (i.e., 250 µA) with a gate-to-source voltage of only –1.04 V, leading to an output-node bias voltage of (3.3 + VGS) = 2.26 V.

While we’re on this subject, I should point out that the bias voltage will be influenced by the width-to-length ratio of the current-mirror transistors. Recall that the saturation-mode relationship between gate-to-source voltage and drain current (if we ignore channel-length modulation) is the following:

ID=12μnCoxWL(VGSVTH)2ID=12μnCoxWL(VGS−VTH)2

We can see that a lower width-to-length ratio will cause the FET to conduct less drain current for the same VGS. Likewise, if the drain current is held constant and the width-to-length ratio is reduced, the magnitude of VGS will have to increase. Theoretically, then, we could fine-tune the bias voltage by adjusting the width-to-length ratio of the current-mirror transistors. Consider the following simulation:

The output-voltage range is restricted by the positive supply voltage and the lowest voltage that allows Q2 to remain in saturation. The condition for saturation is VGD ≤ VTH, so this lower limit is equal to VTH volts below the DC offset of the voltage applied to the gate of Q2. In this circuit we have a DC offset of 0 V and VTH for the NMOS transistors is ~0.5 V, so the lower limit is around –0.5 V. Thus, by reducing the width to 10 µm, we have moved the output node’s bias voltage closer to the middle of the allowable range.

Before we move on, I should point out that in real life the biasing scheme shown above is not practical. The VOUT bias voltage is very important: If it’s too high (or too low), the output’s positive (or negative) signal swing will be restricted. The biasing accomplished in our simulations is reliable only because Q3 and Q4 are perfectly matched.

We can rely on IC manufacturing technology to achieve good matching, but not perfect matching, and any mismatches between the two transistors will lead to variations in the VOUT bias voltage. Thus, real-life implementations employ special biasing circuits that are not so sensitive to manufacturing imperfections.

Two Outputs or One?

You may have noticed that the left-hand VOUT disappeared when we switched from drain resistors to a current mirror. It turns out that an additional (and perhaps somewhat unexpected) benefit of active loading is that it converts the output signal from differential to single-ended without loss of gain.

If you have read The Basic MOSFET Differential Pair, you might remember that we analyzed the overall gain differentially, meaning the output signal was defined as VOUT1 – VOUT2. These two signals are 180° out of phase, so the amplitude of the resulting output signal is doubled.