Monthly Archives: August 2016

Energy Harvesting for Low Power Applications

Energy harvesting is the capture and conversion of small amounts of readily available energy in the environment into usable electrical energy. The electrical energy is conditioned for either direct use or accumulated and stored for later use. This provides an alternative source of power for applications in locations where there is no grid power and it is inefficient to install wind turbines or solar panels.

Other than outdoor solar, no small energy sources provide a great deal of energy. However, the energy captured is adequate for most wireless applications, remote sensing, body implants, RFID, and other applications at the lower segments of the power spectrum. And even if the harvested energy is low and incapable of powering a device, it can still be used to extend the life of a battery.

Energy harvesting is also known as energy scavenging or micro energy harvesting.

Why Harvest Energy

Most low-power electronics, such as remote sensors and embedded devices, are powered by batteries. However, even long-lasting batteries have a limited lifespan and must be replaced every few years. The replacements become costly when there are hundreds of sensors in remote locations. Energy harvesting technologies, on the other hand, provide unlimited operating life of low-power equipment  and eliminate the need to replace batteries where it is costly, impractical, or dangerous.

Most energy harvesting applications are designed to be self-sustaining, cost-effective, and to require little or no servicing for many years. In addition, the power is used closest to the source, hence eliminating transmission losses and long cables. If the energy is enough to power the device directly, the application or device powered by the energy can operate batteryless.

The Building Blocks of an Energy Harvesting System

The process of energy harvesting takes different forms based on the source, amount, and type of energy being converted to electrical energy. In its simplest form, the energy harvesting system requires a source of energy such as heat, light, or vibration, and the following three key components.

  • Transducer/harvester:  This is the energy harvester that collects and converts the energy from the source into electrical energy. Typical transducers include photovoltaic for light, thermoelectric for heat, inductive for magnetic, RF for radio frequency, and piezoelectric for vibrations/kinetic energy.
  • Energy storage: Such as a battery or super capacitor.
  • Power management: This conditions the electrical energy into a suitable form for the application. Typical conditioners include regulators and complex control circuits that can manage the power, based on power needs and the available power.

 

Common Sources of Energy

  • Light energy: From sunlight or artificial light.
  • Kinetic energy: From vibration, mechanical stress or strain.
  • Thermal energy: Waste energy from heaters, friction, engines, furnaces, etc.
  • RF energy: From RF signals.

Energy Harvesting Technologies

Harvesting electrical power from non-traditional power sources using thermoelectric generators, piezoelectric transducers, and solar cells still remains a challenge. Each of these requires a form of power conversion circuit to efficiently collect, manage, and convert the energy from these sources into usable electrical energy for microcontrollers, sensors, wireless devices, and other low-power circuits.

Harvesting Kinetic Energy

Piezoelectric transducers produce electricity when subjected to kinetic energy from vibrations, movements, and sounds such as those from heat waves or motor bearing noise from aircraft wings and other sources. The transducer converts the kinetic energy from vibrations into an AC output voltage which is then rectified, regulated, and stored in a thin film battery or a super capacitor.

Potential sources of kinetic energy include motion generated by humans, acoustic noise, and low-frequency vibrations. Some practical examples are:

  • A batteryless remote control unit: Power is harvested from the force that one uses in pressing the button. The harvested energy is enough to power the low-power circuit and transmit the infrared or wireless radio signal.
  • Pressure sensors for car tires: Piezoelectric energy harvesting sensors are put inside the car tire where they monitor pressure and transmit the information to the dashboard for the driver to see.
  • Piezoelectric floor tiles: Kinetic energy from people walking on the floor is converted to electrical power that can be used for essential services such as display systems, emergency lighting, powering ticket gates, and more.

The Advantages of Actively Loaded MOSFET

images-7The previous article presented the “drain-resistor problem”: We need a larger drain resistor to achieve higher gain, but more drain resistance means a lower DC bias voltage at the output node.

This is a problem because the output voltage is also the MOSFET’s drain voltage, and a lower drain voltage corresponds to a higher risk of pushing the FET out of saturation and into the triode region. We suggested that a current source might resolve this problem by providing high gain without negatively affecting the bias conditions.

The following diagram gives you an idea of the improved biasing situation associated with the use of a current mirror instead of drain resistors.

We have not yet discussed the small-signal resistance of the active-load current mirror, so for now you’ll just have to believe me when I tell you that it is quite high. But as you can see in the circuit diagram, this large small-signal resistance does not apply to the biasing conditions: The bias voltage at the output node is determined by whatever gate-to-source voltage corresponds to Q3’s drain current.

If we consider that this drain current is not particularly large and that Q3’s threshold voltage is maybe 0.7 V, we can guess that the magnitude of VGS will be quite small relative to the high gain resulting from the current mirror’s large small-signal resistance.

Let’s confirm this guess via simulation. Here is the LTspice circuit, with the bias voltage labeled:

(The SPICE models for the FETs can be downloaded here.) This simulation demonstrates that the current mirror’s large small-signal resistance (and thus high gain) does not require a large DC voltage drop. With this particular circuit, Q3 can generate current equal to IBIAS/2 (i.e., 250 µA) with a gate-to-source voltage of only –1.04 V, leading to an output-node bias voltage of (3.3 + VGS) = 2.26 V.

While we’re on this subject, I should point out that the bias voltage will be influenced by the width-to-length ratio of the current-mirror transistors. Recall that the saturation-mode relationship between gate-to-source voltage and drain current (if we ignore channel-length modulation) is the following:

ID=12μnCoxWL(VGSVTH)2ID=12μnCoxWL(VGS−VTH)2

We can see that a lower width-to-length ratio will cause the FET to conduct less drain current for the same VGS. Likewise, if the drain current is held constant and the width-to-length ratio is reduced, the magnitude of VGS will have to increase. Theoretically, then, we could fine-tune the bias voltage by adjusting the width-to-length ratio of the current-mirror transistors. Consider the following simulation:

The output-voltage range is restricted by the positive supply voltage and the lowest voltage that allows Q2 to remain in saturation. The condition for saturation is VGD ≤ VTH, so this lower limit is equal to VTH volts below the DC offset of the voltage applied to the gate of Q2. In this circuit we have a DC offset of 0 V and VTH for the NMOS transistors is ~0.5 V, so the lower limit is around –0.5 V. Thus, by reducing the width to 10 µm, we have moved the output node’s bias voltage closer to the middle of the allowable range.

Before we move on, I should point out that in real life the biasing scheme shown above is not practical. The VOUT bias voltage is very important: If it’s too high (or too low), the output’s positive (or negative) signal swing will be restricted. The biasing accomplished in our simulations is reliable only because Q3 and Q4 are perfectly matched.

We can rely on IC manufacturing technology to achieve good matching, but not perfect matching, and any mismatches between the two transistors will lead to variations in the VOUT bias voltage. Thus, real-life implementations employ special biasing circuits that are not so sensitive to manufacturing imperfections.

Two Outputs or One?

You may have noticed that the left-hand VOUT disappeared when we switched from drain resistors to a current mirror. It turns out that an additional (and perhaps somewhat unexpected) benefit of active loading is that it converts the output signal from differential to single-ended without loss of gain.

If you have read The Basic MOSFET Differential Pair, you might remember that we analyzed the overall gain differentially, meaning the output signal was defined as VOUT1 – VOUT2. These two signals are 180° out of phase, so the amplitude of the resulting output signal is doubled.

What is The Advantage Of Boolean Algebraic Simplification Technique

Digital electronics deals with the discrete-valued digital signals. In general, any electronic system based on the digital logic uses binary notation (zeros and ones) to represent the states of the variables involved in it. Thus, Boolean algebraic simplification is an integral part of the design and analysis of a digital electronic system.

Although Boolean algebraic laws and DeMorgan’s theorems can be used to achieve the objective, the process becomes tedious and error-prone as the number of variables involved increases. This necessitates the use of a suitable, relatively-simple simplification technique like that of Karnaugh map (K-map), introduced by Maurice Karnaugh in 1953.

A Typical K-Map

The K-map method of solving the logical expressions is referred to as the graphical technique of simplifying Boolean expressions. K-maps are also referred to as 2D truth tables as each K-map is nothing but a different format of representing the values present in a one-dimensional truth table.

K-maps basically deal with the technique of inserting the values of the output variable in cells within a rectangle or square grid according to a definite pattern. The number of cells in the K-map is determined by the number of input variables and is mathematically expressed as two raised to the power of the number of input variables, i.e., 2n, where the number of input variables is n.

Thus, to simplify a logical expression with two inputs, we require a K-map with 4 (=22) cells. A four-input logical expression would lead to a 16 (=24) celled-K-map, and so on.

Gray Coding

Further, each cell within a K-map has a definite place-value which is obtained by using an encoding technique known as Gray code.

The specialty of this code is the fact that the adjacent code values differ only by a single bit. That is, if the given code-word is 01, then the previous and the next code-words can be 11 or 00, in any order, but cannot be 10 in any case.

In K-maps, the rows and the columns of the table use Gray code-labeling which in turn represent the values of the corresponding input variables. This means that each K-map cell can be addressed using a unique Gray Code-Word.

These concepts are further emphasized by a typical 16-celled K-map shown in Figure 1, which can be used to simplify a logical expression comprising of 4-variables (A, B, C and D mentioned at its top-left corner).

Here the rows and the columns of the K-map are labeled using 2-bit Gray code, shown in the figure, which assigns a definite address for each of its cells.

For example, the grey colored cell of the K-map shown can be addressed using the code-word “0101” which is equivalent to 5 in decimal (shown as the green number in the figure) and corresponds to the input variable combination A̅BC̅D or A+B̅+C+D̅, depending on whether the input–output relationship is expressed in SOP (sum of products) form or POS (product of sums) form, respectively.

Similarly, AB̅CD or A̅+B+C̅+D̅ refers to the Gray code-word of “1011”, equivalent to 11 in decimal (again, shown in green in the figure), which in turn means that we are addressing the pink-colored K-map cell in the figure.

K-Map Simplification Technique

With this general idea of K-maps, let us now move on to the procedure employed in designing an optimal (in terms of the number of gates used to realize the logic) digital system. We’ll start with a given problem statement.

Example 1:

Design a digital system whose output is defined as logically low if the 4-bit input binary number is a multiple of 3; otherwise, the output will be logically high. The output is defined if and only if the input binary number is greater than 2.

Step 1: Truth Table / Canonical Expression Leading to Min- or Max-Terms

The first step in designing any digital system is to have a clear idea of the variables involved in the process, along with their state-values. Further, depending on the problem statement, we have to arrive at the number of output variables and their values for each and every combination of the input literals, which can be conveniently represented in the form of a truth table.

In the given example:

Number of input variables = 4, which we will call A, B, C and D.

Number of output variables = 1, which we will call Y

where

         Y = Don’t Care, if the input number is less than 3 (orange entries in the truth table)

         Y = 0, if the input number is an integral multiple of 3 (green entries in the truth table)

         Y = 1, if the input number is not an integral multiple of 3 (blue entries in the truth table)

Note that, in addition to the input and output columns, the truth table also has a column which gives the decimal equivalent of the input binary combination, which makes it easy for us to arrive at the minterm or maxterm expansion for the given problem. Thus for the given example,

Minterm expansion will be  ∑m(4,5,7,8,10,11,13,14) + ∑d (0,1,2)

Maxterm expansion will be ∏M(3,6,9,12,15) · ∏D (0,1,2)

However, sometimes the logical expression which is to be simplified might be directly given in terms of SOP or POS forms. In this case, the requirement for the truth table can be overlooked provided that we express the given expression in its canonical form, from which the corresponding minterms or maxterms can be obtained.

Step 2: Select and Populate K-Map

From Step 1, we know the number of input variables involved in the logical expression from which size of the K-map required will be decided. Further, we also know the number of such K-maps required to design the desired system as the number of output variables would also be known definitely. This means that, for the example considered, we require a single (due to one output variable) K-map with 16 cells (as there are four input variables).

Next, we have to fill the K-map cells with one for each minterm, zero for each maxterm, and X for Don’t Care terms. The procedure is to be repeated for every single output variable. Hence for this example, we get the K-map as shown in Figure 2.