Monthly Archives: April 2016

KNow More About Drain to Source Resistance

One of the most prominent specifications on datasheets for discrete MOSFETs is the drain-to-source on-state resistance, abbreviated as RDS(on). This RDS(on) idea seems so pleasantly simple: When the FET is in cutoff, the resistance between source and drain is extremely high—so high that we assume zero current flow. When the FET’s gate-to-source voltage (VGS) exceeds the threshold voltage (VTH), it is in the “on state,” and the drain and source are connected by a channel with resistance equal to RDS(on). However, if you are familiar with the actual electrical behavior of a MOSFET, you should readily recognize that this model doesn’t accord with the facts.

First, the FET does not really have an “on state.” When not in cutoff (we’re ignoring subthreshold conduction here), the FET can be in the triode region or the saturation region. Each of these regions has its own current–voltage relationship. However, we can safely assume that “on state” corresponds to the triode region because RDS(on) is relevant in the context of switch circuits, not small-signal amplifiers, and switch circuits—e.g., for driving a motor or controlling a relay—employ the cutoff and triode regions.

But still, the triode region is governed not by a mere resistance but by a rather complicated equation:


(This is for an NMOS device; a PMOS device would have µp instead of µn.) However, if we ignore the VDS2term, the equation can be simplified as follows:


Now we do indeed have a linear (i.e., resistive) relationship between drain-to-source current (ID) and drain-to-source voltage (VDS). However, the “resistance” is not constant, as in the case of a mere resistor; rather, the resistance corresponds to


This brings us to an important point about RDS(on): it is influenced by the gate-to-source voltage. Here’s an example taken from the datasheet for Fairchild’s NDS351AN MOSFET:

The typical threshold voltage for this part is given as 2.1 V. If you look quickly at the VTH spec and very quickly at the RDS(on) spec, you might think that you can drive this FET with a 3.3 V logic signal and achieve the advertised on-state-resistance performance. This would be a bit careless considering that the datasheet clearly specifies the gate-to-source voltage that corresponds to the RDS(on) spec; however, one or two RDS(on)/VGS data points do not convey the extreme increase in on-state resistance that applies to gate-to-source voltages that are actually well above the typical VTH. So the morals of the story are 1) remember that on-state (i.e., triode-region) resistance is dependent on VGS and 2) for detailed information refer to the plot of RDS(on) vs. VGS.

Furthermore, on-state resistance is not equal to the resistance expressed by the triode-region equation given above. The latter is the resistance of the MOSFET’s channel, whereas on-state resistance encompasses other sources of resistance—bond wires, the epitaxial layer, etc. Resistance characteristics are influenced by manufacturing technology, and the respective contributions of the different components of RDS(on) vary according to the voltage range for which a particular device is intended.

Analysis with an Oscilloscope

The oscilloscope is an invaluable diagnostic instrument that can be used to troubleshoot problem circuits, verify product design before delivery to consumers, and reverse-engineer products for “hacks”.

We will explore the various uses of an oscilloscope using the Tektronix MDO3104 that was provided by Tektronix. Part 1 will show the versatility of the current generation of oscilloscopes.

Getting a Scope

When preparing articles, we typically provide a link to purchase the parts required from various vendors. Due to the high cost of the machine used in this article, it seemed prudent to find an option for readers to acquire a machine in some other manner. If you cannot afford to purchase a new oscilloscope, you can rent, rent-to-own, lease, finance, or purchase used machines from companies such as Microlease.

A Note Before We Begin

All examples in this article are based on the Tektronix MDO3104 oscilloscope.

While preparing this article I contacted several test instrument makers —Rigol and BK Precision also offered to make test instruments available for this article and I would like to thank all companies for their generosity. They are all world-class instruments.

This article is not intended to be a how-to guide to the Tektronix MDO3104. It is meant to show you the various capabilities and functions of most mid-range oscilloscopes through the use of the Tektronix MDO3104 as an example.

I will show the steps needed to use the machine I have—it is left to the reader to see the documentation on their specific scope for specific key-presses and menu-options. I use bold to indicate physical manipulation of the scope through knob-turn or button-press, and quotation marks to indicate a menu choice.

Oscilloscope Displays

Oscilloscopes allow us to determine relationships between certain variables in electrical circuits. Early oscilloscopes were only able to show the relationship that exists between potential difference and time. Today’s oscilloscopes continue the tradition of measuring voltage vs. time while also providing an extensive collection of sophisticated data-analysis capabilities, display features, and triggering options.

To understand what electrical relationships exist in your circuits, you have to know how to interpret what is presented to you.

This is a typical single waveform display in an oscilloscope, showing the time on the horizontal axis and potential difference on the vertical axis.

In the lower left part of the image, you will see  ① 500mV

That indicates two things:

  • Channel 1 is displayed on the oscilloscope in yellow.
  • For channel one each grid rectangle corresponds to 500 mV in the vertical direction. So we have “500 millivolts per division” with 8 vertical rectangle visible, and thus

    visible in the vertical direction

In the bottom left, you will see another box that says AFG Sine 100.00kHz 1.0000 Vpp:

  • AFG Indicates the Arbitrary Function Generator is active (I used it to create this waveform)
  • Sine is the shape of the waveform
  • 100.000 kHz is the frequency of the waveform: 100,000 cycles each second.
  • 1.0000 Vpp is the amplitude of the transmitted waveform.

In the bottom-center there is another box with:

  4.00 µs                      5.00 GS/s      ① ∫       
  T →▼0.000000 s     1M points      0.00V
  • 4.00 µs is the value of each rectangle in the horizontal direction:  “4 microseconds per division.”  The display includes 10 rectangles, so
    4.00μs1 division×10divisions=40 μs4.00μs1 division×10divisions=40 μs

    of time is visible across the entire screen.

  • The oscilloscope is recording 5.00 GS/s, i.e.,

    samples per second.

  • Channel 1 is used to control the triggering of the waveform.
  • Triggering occurs on the rising edge of the channel 1 waveform.
  • The image is centered at T →▼0.000000 s from the trigger point.
  • 1 million (1 M) data points will be collected.
  • Triggering occurs when a rising signal passes through 0 V.

How to Make Basic Measurements with an Oscilloscope

To illustrate just how far these oscilloscopes have come over the past few decades, I will begin by showing you how many different ways the oscilloscope can be used to make basic measurements of frequency (or period) and peak-to-peak amplitude.

Activate the Arbitrary Function Generator

Begin by connecting oscilloscope channel 1 to the Arbitrary Function Generator (AFG) BNC connector on the back of the scope.  Activate the Arbitrary Function Generator by pressing the AFG button directly above the Channel 1 probe input.  Press the first bottom menu button below “Waveform” and use rotary knob Multipurpose a to select “Ramp.”

Turn on Channel 1

Press the Channel 1 button to activate it.  Rotate the Horizontal Scale knob clockwise to adjust the scale to spread out a complete wave over most of the screen.  Use the Horizontal Position knob to adjust its location on the screen if you like.

Using the Graticule to Make Measurements

The lines on an oscilloscope display are called a graticule.  There are major and minor gridlines (or dots) that are used to measure waveforms.  Major gridlines are displayed as solid or dotted lines that run the width or height of the oscilloscope screen.  The voltage and time that correspond to the divisions formed by the major gridlines are shown at the bottom of the display.  Minor gridlines are subdivisions between major gridlines.  There are usually 4 or 5 subdivisions between gridlines.  In the following example, I used theHorizontal Position rotary dial to move the waveform so that the positive peaks of the waveform line up with major vertical gridlines.

What is the flip flop say

This article covers the steps involved in converting a given T flip-flop into SR-, JK-, and D-type flip-flops. We also present a verification technique for these conversions; the verification process allows us to ensure that the designed systems provide the desired functionality.

Previous Articles in This Series

Please refer to the previous parts in this series, particularly the first two, for a detailed explanation of the process:

  • Introduction to the Conversion of Flip-Flops
  • SR-to-D and SR-to-T Flip-Flop Conversions
  • Conversion of JK Flip-Flops
  • Conversion of D Flip-Flops

Conversion of a T to an SR Flip-Flop

In order to convert a given T flip-flop into SR-type, we need to combine the information presented in the SR flip-flop’s truth table and the information in the T flip-flop’s excitation table into a common table. This can be referred to as a T-to-SR conversion table and is as shown in Figure 1.

Notice the don’t care (X) entries in the last two rows of the conversion table’s “T input” column. These indicate that when both inputs (S and R) are driven high, the output of the SR flip-flop is unpredictable (owing to the “race around condition”).

Next, we should express the input of the given flip-flop in terms of the present-state, Qn, and the input(s) of the desired flip-flop. This can be done by using a suitable simplification technique, such as the K-map (discussed in detail in a separate article).

Figure 2 shows that the simplified logical expression for the T input in terms of S, R, and Qn is SQ̅n + RQn.

Designing Your System

To make the given T flip-flop functionally equivalent to the desired SR flip-flop, we need to AND Q̅n with the user-defined input S and also AND Qn with the user-provided input R. The results of these AND operations are then ORed together.

Thus, we require two AND gates and one OR gate to convert the T flip-flop to an SR-type, as shown in Figure 3.


Having designed the system, we will now verify that the conversion process was successful. This can be accomplished by means of the truth table–based verification technique. The process involves comparison between the truth table of the desired (SR) flip-flop and the verification table for the T-to-SR conversion, as shown in Figure 4.

Figure 4 shows that the values in the first, second, third, and eighth columns (shaded in beige) of the T-to-SR verification table are consistent with those in the SR flip-flop’s truth table. Thus, the conversion process was successful. The last two rows at first seem inconsistent, but they are indeed acceptable because an SR flip-flop’s outputs can be either high or low when both inputs are logic high. Actually, the converted T flip-flop is better than an SR flip-flop because it has predictable output states even for the invalid input combination.

Conversion of a T to a JK Flip-Flop

We begin with the T-to-JK conversion table (see Figure 5), which combines the information in the JK flip-flop’s truth table and the T flip-flop’s excitation table.

Next, we need to obtain the simplified Boolean expression for the T input in terms of J, K, and Qn.

Figure 6 shows the expression for the T input as JQ̅n + KQn. This means that to convert the T flip-flop into a JK flip-flop, the T input is driven by the output of a two-input OR gate which has as inputs

  1. J ANDed with the negation of the present-state Qn, i.e., Q̅n
  2. K ANDed with the present-state, Qn

Thus, we will need two AND gates and one OR gate, as shown in Figure 7.

The final step is to verify whether the system behaves as we expect it to. This can be done using a T-to-JK verification table, shown in Figure 8. Here we can compare the entries in the verification table to the truth table of the JK flip-flop.

The entries in the first, second, third, and eighth columns (shaded in beige) of the T-to-JK verification table agree with those in the truth table of the JK flip-flop. This indicates that the given T flip-flop has become functionally equivalent to the desired JK flip-flop.

Conversion of a T to a D Flip-Flop

We begin by writing the T-to-D conversion table (see Figure 9).

Once this is done, we need to express the input, T, in terms of the user-defined input, D, and the flip-flop’s present-state, Qn. We will again use the K-map simplification technique.

Figure 10 shows that, in order to make the given T flip-flop functionally equivalent to a D flip-flop, we need to drive its input pin, T, with the output of an XOR gate whose inputs are D and Qn. This will lead to the new digital system shown in Figure 11(a). Figure 11(b) shows a system which is functionally equivalent to that of Figure 11(a) but is designed using only NOT, AND, and OR gates.